Senior RTL Design Engineer

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Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.

Job Type: Contract

Length of Assignment: 12+ Months

Location: Remote or Burlingame, CA

We are seeking an experienced and highly motivated Digital Design Engineer/ASIC Chip Lead to contribute to the development and integration of cutting-edge SoC solutions. This role involves architecture definition, RTL development, integration, and support from concept to production. You will work with cross-functional teams including verification, validation, and FPGA prototyping groups to bring high-performance digital IPs and systems to life.

Contribute to the development of efficient Architectures and contribute to ASIC digital Architecture, design and verification

Understand Design for Verification concepts

Drive the top-level Architecture definition and develop the necessary RTL

Drive the chip-level integration, verification plan development and verification

Supervise the RTL-to-GDS flow and assist with synthesis and timing closure

Support the test program development, chip validation and chip life until production maturity

Work with FPGA engineers to perform early prototyping

Support hand-off and integration of blocks into larger SOC environments

Assist with Algorithm analysis, verification and improvement

Contribute to ASIC digital architecture, design and verification

Must Have:

4+ years of experience as a Digital Design Engineer and/or a Chip Lead

Experience in RTL coding, synthesis and/or SoC Integration

BS Electrical Engineering/Computer Science or equivalent experience

Experience with UPF based simulation flow

System Verilog OVM/UVM experience

Tcl and Python (or similar) Scripting experience

Experience in SoC integration and ASIC architecture

Wish List/Nice to Have:

Experience in DFT/Testability requirement and test program definition

Experience using High Speed interfaces like PCIe, USB, MIPI

Experience with Power Aware GLS flow

MSEE/CS or equivalent experience

Education

Bachelor degree in Electrical/Computer Engineering or Computer Science

Master's Degree preferred but not required

Skills:

• RTL Coding
• Synthesis and/or SoC Integration
• systemVerilog Coding
• Health, Dental and Vision Insurance
• 401k

Seniority level

• Seniority level Mid-Senior level

Employment type

• Employment type Contract

Job function

• Industries Semiconductor Manufacturing

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Inferred from the description for this job

Vision insurance

401(k)

Medical insurance

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