Senior Staff Physical Design Engineer - Static Timing Analysis

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

At Marvell, we build semiconductor solutions that move, store, process, and secure the worlds data. As part of our Central Data Center Engineering team, youll help shape the future of compute infrastructure by developing high-performance ASICs that power next-generation data centers. Were looking for passionate engineers who thrive in a collaborative and innovative environment.

We are seeking a Senior Staff Physical Design Engineer Static Timing Analysis (STA) to join our growing team. In this role, you will be responsible for timing closure of large, complex ASIC designs from RTL to final signoff. You will work closely with cross-functional teams including RTL design, synthesis, and physical implementation to ensure on-time and high-quality tape-outs.

What You Can Expect

• Perform full-chip and block-level static timing analysis for advanced ASIC designs
• Develop, maintain, and optimize timing constraints, methodologies, and automation scripts
• Own timing closure across all stages of the design flow: RTL, synthesis, physical implementation, and signoff
• Debug and resolve complex timing violations and drive design fixes
• Collaborate closely with design, synthesis, and physical design teams to meet performance, power, and area (PPA) goals
• Provide guidance on design partitioning, floorplanning, and timing budgeting strategies
• Contribute to design reviews and provide expert insights for design improvements

What We're Looking For

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related discipline
• 8+ years of hands-on experience in STA and timing closure for large-scale ASIC designs
• Strong proficiency with EDA tools such as Synopsys PrimeTime, PrimeTime SI, and/or Cadence Tempus
• Deep understanding of timing concepts, constraints development, and signoff methodologies
• Demonstrated success in driving complex designs to timing closure
• Excellent problem-solving skills and strong attention to detail
• Strong communication skills and proven ability to work effectively in a collaborative team environment

• Preferred Experience:

• Familiarity with scripting languages such as Tcl, Perl, or Python
• Experience with hierarchical timing and multi-mode/multi-corner (MMMC) analysis
• Knowledge of data center ASIC architecture or high-performance computing systems

Expected Base Pay Range (USD)

124,420 - 186,400, $ per annum

The successful candidates starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .

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