ASIC SoC Architect

Life is Short. Solve Hard Problems with Cool People. Our client is the Goldilocks of the spirit and growth of a startup, with a financial footing and safety of a stable corporation. They are seeking an ASIC SoC Architect. Solve the Problem, Not the Symptom. Our client designs and deploys secure system solutions through novel CPU design, crypto cores, purpose-built system-on-a-chip architectures and hardened operating systems. Our solutions are the foundation for how military systems and US critical infrastructure will remain safe and secure through unpredictable operating environments of the future. We need smart people like you to join us in solving hard problems that matter. What You'll Get to Do: Be the technical lead of a cross-functional team (hardware engineering, software developers, verification engineers) to define, design, simulate, fabricate and iterate a RISC-V Application-Specific Integrated Circuit (ASIC) System on a Chip (SoC) product for defense and commercial applications based on Idaho Scientific's Helios secure RISC-V CPU. The RTL already exists - the major task is transferring that capability to a functioning, production-ready ASIC. Tasks ahead will follow the latest industry-standard design methodologies to finalizing the RTL code, synthesis, place-and-route and verification. Be the primary technical interface with pilot customers, the internal engineering team and external subcontracted specialists to define and document product features, use cases, and functional requirements Finalize and maintain the microarchitecture definition and associated documentation (complete ASIC specification, requirements and verification plan), including performance, I/O, power consumption, area utilization, recurring cost and security functionality Develop and oversee the implementation of a comprehensive verification strategy including testbench development, functional verification and performance verification. Ensure the verification team has adequate coverage and highest probability of first-pass success. Continuously evaluate new ASIC technologies, design methodologies for possible incorporation into the design. Prioritize and schedule a product roadmap that defines the inclusion of technical features to align with timing of market need and competitive advantage Decompose the product plan into actionable and trackable tasks, including design reviews and demonstrations that the team can execute to Identify strategic partners to assist in the development, marketing, and sustainment of the product to augment internal capabilities Required Qualifications & Experience US Citizenship Proven work experience designing and fabricating an ASIC 8 or more years of ASIC design and architecture experience Solid technical background with understanding and/or hands-on experience in ASIC product development Bachelor's Degree in Computer Engineering, Computer Science, Electrical Engineering or related field Strong proficiency in RTL coding (Verilog or VHDL), ASIC design flow, and EDA tools In-depth knowledge of ASIC architectures, including digital logic design, clocking methodologies, and low-power design techniques Experience with industry-standard ASIC design methodologies (e.g., RTL synthesis, place-and-route, timing closure) and verification methodologies (e.g., UVM, SystemVerilog) Strong analytical and problem solving skills Extreme attention to detail Strong problem solving skills and willingness to roll up one's sleeves to get the job done Skilled at working effectively with cross functional teams Preferred Qualifications & Experience US Security Clearance, Active or current within the last two years In-depth understanding of microprocessor market and processor architectures Working knowledge of applied cryptography and cyber security topics Experience applying principles of cyber security to operational technology and embedded systems Location Boise, Idaho or Salt Lake City, Utah Benefits and Perks Competitive Pay Flexible Work Schedule Health Benefits and Insurance Retirement fund contributions Profit Sharing Generous Paid Time Off Policy