Timing Design Engineer

Job Summary

Summary Posted: Jun 02, 2025 Role Number: 200607222 At Apple, we work every single day to craft products that enrich peoples lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and hardworking Timing Design Engineer. As a member of our multifaceted group, you will have the outstanding and phenomenal opportunity to craft upcoming products that will delight and encourage millions of Apples customers every day. In this role, you will be at the center of a PHY design effort collaborating with architecture, CAD, logic design teams, with a critical impact on delivering outstanding PHY designs. You will be directly involved in timing closure and/or physical designs of outstanding PHY design.

Description

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis

EEO Notice

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .