Asic Design Engineer, Silicon

ApplyBachelor's degree in Electrical or Computer Engineering or equivalent practical experience.6 years of experience with ARM-based System on a chip (SoCs), interconnects, and Application-Specific Integrated Circuit (ASIC) methodology.5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture.Experience with a coding language like Python or Perl.Preferred qualifications:Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.6 years of industry experience with Intellectual Property (IP) design.Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC).Experience with methodologies for low power estimation, timing closure, synthesis.About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.You'll contribute to the innovation behind products loved by millions worldwide.Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.In this role, you will design foundation and chassis IPs (e.g., Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU), and other peripherals) for Pixel System on a chip (SoCs).You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc., to specify and deliver a quality Register-Transfer Level (RTL).You will solve technical problems with micro-architecture, low power design methodology, and evaluate design options with performance, power, and area in mind.Google's mission is to organize the world's information and make it universally accessible and useful.Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences.We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful.We aim to make people's lives better through technology.ResponsibilitiesParticipate in test planning and coverage analysis.Develop Register-Transfer Level (RTL) implementations that meet power, performance, and area goals.Participate in synthesis, timing/power closure, and FPGA and silicon bring-up.Perform Verilog/SystemVerilog RTL coding, functional and performance simulation, debug, and checks (Lint/CDC/FV/UPF).Create tools/scripts to automate tasks and track progress.Google is proud to be an equal opportunity and affirmative action employer.We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing equal employment opportunities regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related conditions (including breastfeeding), expecting or parents-to-be, criminal histories, or any other legally protected basis.See also Google's EEO Policy, Know your rights, Belonging at Google, and How we hire.Google is a global company, and English proficiency is required for all roles unless otherwise stated.We do not accept agency resumes; please do not forward resumes to our jobs alias or employees.Google is not responsible for fees related to unsolicited resumes.#J-18808-Ljbffr