Senior ASIC Front End (RTL) Design Engineer

Senior ASIC Front End (RTL) designer

As a front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, and software teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of wafer-scale integration.

Responsibilities

• Drive all aspects of WSE design, including Functional Specification, Micro-architecture, RTL development, Synthesis.

• Work closely with PD team members for design closure to meet PPA goals

• Work closely with DFT team members to develop optimal test of wafer-scale designs

• Work with software teams to understand opportunities to deliver optimal performance and feature set for the product

• Debug silicon-level functional, timing, and power issues during wafer bring up

Requirements

• Master's degree in Computer Science, Electrical Engineering, or equivalent

• 10+ years of experience in delivering complex, high performance high quality RTL designs

• Demonstrated experience in high-performance computing, networking, machine learning or related fields

• Proven track record of multiple silicon success.

• Experience with Front End Chip integration and third-party IP integration

• Experience collaborating with hardware and software teams to deliver successful silicon

• Knowledge of high-speed memory interfaces, CPU interfaces and Serdes technology

• Working knowledge of scripting tools : Python, TCL

Desired skills

• Networking stack experience including TCP/IP, RDMA and Ethernet is a plus

• Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus