Silicon RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

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THE ROLE:

Join our elite Security IP (SECIP) team as an RTL Design Engineer, where your talents will contribute to groundbreaking innovations in embedded micro-processor (MP) subsystems and high-performance hardware accelerators. Here, you'll be at the forefront of designing and verifying vital components that enhance performance and functionality across a diverse range of System on Chip (SoC) products, solidifying our leadership in the industry. Your work will empower all AMD business units, from client computers and servers to discrete graphics and gaming solutions. As a key player in block-level RTL design and subsystem-level integration, you will directly influence cutting-edge applications like security policy management, cryptography, data compression, high throughput DMA, and power management. If you're ready to shape the future of technology and elevate your career in a collaborative and innovative environment, we want to hear from you! Join us in making a real difference in the world of security and performance.

THE PERSON:

Are you a visionary hardware RTL design engineer eager to make a significant impact on cutting-edge technology? Join our dynamic team where your technical expertise will shine as you take full ownership of exciting block-level IP and MP subsystems design and verification projects. We seek a forward-thinking innovator who is not only passionate about optimizing workflows but also thrives in a fast-paced environment filled with diverse challenges. Your ability to anticipate and resolve technical issues will be key to driving our success, while your mentorship will empower your colleagues to reach new heights. If you excel in problem-solving, possess keen attention to detail, and are an exceptional communicator, we invite you to bring your skills to a collaborative setting where your contributions will truly make a difference. Embrace the opportunity to advance your career while working on groundbreaking technologies—your future begins here!

KEY RESPONSIBILITES:

• Develop and maintain block level RTL IP and MP subsystems’ feature spec, micro-architecture, synthesizable RTL design methodology and infrastructure
• Develop and debug RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests, and achieve design feature closure (feature spec vs. coverage metrics)
• Triage regressions, debug specific simulations, analyze coverage, and work/resolve technical issues with design, verification, and other teams to achieve design feature and design rule closures (linting, timing, DFT, DFP and other rules)
• Participate in verification testbench and test plan specification, influence testbench architecture development (design for verification aspect), review and improve feature and coverage test plans
• Debug and resolve integration issues with SoC Integration, SoC DV and post-silicon validation teams
• Provide technical leadership in IP functionality and design methodology development as well as critical problem resolution if as advanced level team members

PREFERRED EXPERIENCE:

• Proven understanding of CPU and MP subsystem architecture, Datapath accelerator RTL microarchitecture, as well as FPGA based simulation or emulation methodology
• Proficient in Verilog, System Verilog (an extra asset), and scripting (using TCL, Ruby, Perl, Python and Make file)
• Excellent knowledge of state-of-the-art RTL design and verification methodology and best practices, and C-DPI test design
• Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
• Proven experience with ASIC design tools: synthesis, linting, simulation, debugging, power aware simulation, etc.
• Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates

ACADEMIC CREDENTIALS:

• Bachelor’s degree or master’s degree in electrical engineering, Computer Engineering, or Computer Science, or possibly a related field

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Benefits offered are described: AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.