ASIC RTL Design Engineer

Job details are shared below: Job Title: ASIC/RTL Design Engineer Location: San Jose, CA (onsite 4 days a week) Job Duration: 12+ months Contract with potential for conversion Primary Skills: 5-6+ years' experience designing RTL blocks for an SoC Experience or strong understanding of SystemVerilog, analyzing existing designs, and making modifications Experience or familiarity with tools used by ASIC engineers like Lint, CDC, STA, etc. Proven track record of ASIC design on multiple production tape-outs Experience in designing RTL blocks for an SoC Experience in integrating ASIC IP into an SoC Experience with synthesis, static timing analysis, and optimizations Nice to have: Experience with Scripting languages such as PERL, Python, or Tcl Experience writing timing constraints and exceptions Experience with automation using Scripting techniques Knowledge of power-saving techniques Experience with Arm architecture and protocols like APB, AXI, CHI Experience with interconnect design Ability to develop clear and concise engineering documentation Strong communication skills, both verbal and written Responsibilities: Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet requirements Collaborate with architecture and hardware teams to understand requirements Work with verification and physical design teams to ensure high-quality design and successful tape-out Design and implement logic functions for test and debug Participate in silicon bring-up for owned features Contribute to solving complex problems across teams Implement automation to increase team efficiency Qualification: Bachelor's degree in a relevant field Please respond promptly to expedite the interview process. I will contact you if further details are needed. Amit Bundele Technical Recruiter Phone: 669-#-# Email: (see below) San Jose, California www.netpolarity.com