AR Subsystem Performance Architect, Reality Labs Silicon

As a member of the RL subsystem architecture team you will play a key role in performance architecture and modeling. You will analyze our key workloads (graphics rendering, display, audio, computer vision, or color imaging) and collaborate with IP architects and execution engineers to architect subsystems that are SW usable, performant and power efficient. You will also act as a key point-of-contact representing the team with varying internal and external partners, in a highly cross-functional environment, delivering on proof of concepts for workloads and other significant demands.

**Required Skills:**

AR Subsystem Performance Architect, Reality Labs Silicon Responsibilities:

1. Identify performance opportunities for optimization and collaborate with hardware teams to solidify Hardware-Software (HW-SW) co-design

2. Own performance models for system interconnect, cache, memory hierarchy analysis

3. Own Subsystem Network on Chip (NoC) architecture specification, design and characterization

4. Lead Intellectual Property (IP) performance bottleneck analysis using traffic traces from pre/post silicon platforms

5. Lead analysis and configuration of subsystem caches for optimal performance

6. Drive next generation workload analysis for performance across the workloads of interest

7. Drive IP latency hiding features and Quality of Service (QoS) recommendations for each compute engine

8. Collaborate with various partners to deliver documentation and proof of concepts for workloads running on these subsystems

9. Identify and manage appropriate comparative analysis to ensure the workloads are targeting state of the art

**Minimum Qualifications:**

Minimum Qualifications:

10. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

11. 6+ years of performance modeling experience with programming (C/C++ or SystemC-TLM) and scripting (Python)

12. 5+ years of experience evaluating architectural trade-offs in performance, power, and other key performance metrics

13. 4+ years of expertise with post-silicon to pre-silicon correlation analysis

14. 2+ years of experience with System on Chip (SoC) Architecture, NoCs, memory subsystems, and heterogeneous compute principles

**Preferred Qualifications:**

Preferred Qualifications:

15. 3+ years of experience with bare-metal programming, micro-benchmarking, etc

16. 3+ years of experience deconstructing a problem, designing performance experiments, analyzing and visualizing data, and drawing conclusions for modeling and subsystem architecture

17. 2+ years of experience with power concepts and low power design principles

18. Expertise collaborating and communicating effectively in a matrix environment, as well as taking initiative as the point-of-contact representing your team with internal and external partners

19. Expertise in at least one relevant area: Audio, Display, Rendering, Computer Vision, or Imaging

20. Expertise with developing and utilizing telemetry solutions to analyze and profile workloads

**Public Compensation:**

$142,000/year to $203,000/year + bonus + equity + benefits

**Industry:** Internet

**Equal Opportunity:**

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

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