Senior CPU Design Engineer
Actively hiring
Job type :
Full-time
Department :
Hardware
Workplace type :
On-site
Job Details
Drive the Next Wave of Computing Innovation at MIPS
At MIPS, we're shaping the future of compute architecture with advanced IP that powers a wide range of applications. We take a disciplined, methodical approach to designing scalable, energy-efficient solutions that meet demanding power, performance, and area goals.
Our team spans from architecture, performance modeling, design, verification, implementation to software and software optimization for our customers. The team thrives on collaboration, technical depth, and a culture of mutual respect. We value diverse perspectives and practical experience, and we know that excellence is built through thoughtful teamwork and a commitment to the highest engineering standards.
We're seeking a CPU RTL design engineer with prior experience in creating structural RTL for one of the following: CPU, GPU, DSP, Interconnects, memory controllers or compute accelerators.
As part of our team, you'll have the opportunity to take ownership of CPU functional blocks and implement RTL, and work with verification and physical design engineers to ensure adherence to functional and physical project requirements. You'll also mentor junior engineers in the art of RTL design.
Our flexible hybrid work modelthree days in the office, two remotesupports both in-person collaboration/mentoring and focused development time.
Join us and put your skills, insight, and passion to work to redefine what's possible
Description
As a CPU design engineer you own or participate in the following:
RTL design of one or many functional blocks based on the microarchitectural specification. Ownership includes the RTL design, implementation and convergence of the block to project requirements (performance, timing, power, area, schedule)
Support of the verification team for test bench development, test plan development and test content development, including performance verification
Work with physical design teams, and design for testability teams to implement and converge physical design and testability
Minimum Qualifications
Minimum BS and 5+ years of relevant industry experience
Experience in structural data path and/or control logic design
Experience in at least one area of CPU microarchitecture
Experience with Verilog, System Verilog, or VHDL
Demonstrated debug capabilities with commercial simulators and wave viewing tools
Experience in working with physical design team on convergence for PPA
Good verbal and written communication skills to interface with performance modeling, verification and physical design team
Preferred Qualifications
Experience with low power design techniques
Experience using scripting languages and regular expressions
Programming experience with assembly, C, or C++
Actively hiring
Job type :
Full-time
Department :
Hardware
Workplace type :
On-site
Job Details
Drive the Next Wave of Computing Innovation at MIPS
At MIPS, we're shaping the future of compute architecture with advanced IP that powers a wide range of applications. We take a disciplined, methodical approach to designing scalable, energy-efficient solutions that meet demanding power, performance, and area goals.
Our team spans from architecture, performance modeling, design, verification, implementation to software and software optimization for our customers. The team thrives on collaboration, technical depth, and a culture of mutual respect. We value diverse perspectives and practical experience, and we know that excellence is built through thoughtful teamwork and a commitment to the highest engineering standards.
We're seeking a CPU RTL design engineer with prior experience in creating structural RTL for one of the following: CPU, GPU, DSP, Interconnects, memory controllers or compute accelerators.
As part of our team, you'll have the opportunity to take ownership of CPU functional blocks and implement RTL, and work with verification and physical design engineers to ensure adherence to functional and physical project requirements. You'll also mentor junior engineers in the art of RTL design.
Our flexible hybrid work modelthree days in the office, two remotesupports both in-person collaboration/mentoring and focused development time.
Join us and put your skills, insight, and passion to work to redefine what's possible
Description
As a CPU design engineer you own or participate in the following:
RTL design of one or many functional blocks based on the microarchitectural specification. Ownership includes the RTL design, implementation and convergence of the block to project requirements (performance, timing, power, area, schedule)
Support of the verification team for test bench development, test plan development and test content development, including performance verification
Work with physical design teams, and design for testability teams to implement and converge physical design and testability
Minimum Qualifications
Minimum BS and 5+ years of relevant industry experience
Experience in structural data path and/or control logic design
Experience in at least one area of CPU microarchitecture
Experience with Verilog, System Verilog, or VHDL
Demonstrated debug capabilities with commercial simulators and wave viewing tools
Experience in working with physical design team on convergence for PPA
Good verbal and written communication skills to interface with performance modeling, verification and physical design team
Preferred Qualifications
Experience with low power design techniques
Experience using scripting languages and regular expressions
Programming experience with assembly, C, or C++
Job ID: 484860623
Originally Posted on: 7/11/2025
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