Remote ASIC Design Engineer

A client of Insight Global is looking for a Remote ASIC Design Engineer to join their team of 15. In this role, you will be responsible for the Design for Testability (DFT) aspects of ASIC design, which requires a thorough understanding of digital design concepts. Your responsibilities will include overseeing the entire ASIC development process, ensuring that all design elements are optimized for testability. You must be knowledgeable in VHDL, Verilog, or SystemVerilog RTL coding, and demonstrate a high level of proficiency in DFT methodologies. Additionally, you will be expected to operate effectively within a team environment, collaborating with various teams to achieve the project's goals. This collaboration will involve regular communication and coordination with other team members, sharing insights and feedback to enhance the overall design process. Your role will be crucial in ensuring that the final product meets all design and testability standards, contributing to the success of the project.

Compensation: $70/hr. -- 76/hr. Exact compensation may vary based on several factors, including skills, experience, and education. Benefit packages for this role will start on the 1st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.

We are a company committed to creating inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity employer that believes everyone matters. Qualified candidates will receive consideration for employment opportunities without regard to race, religion, sex, age, marital status, national origin, sexual orientation, citizenship status, disability, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to Human Resources Request Form ( . The EEOC "Know Your Rights" Poster is available here ( .

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Skills and Requirements

Bachelors degree with 8 years of experience, a Masters degree with 6 years of experience

Experience in full product life cycle of ASIC Design

Experience with Cadence and/or Mentor test insertion and ATPG tools

Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG)

Experience with memory BIST and logic BIST

Experience working with test engineers to implement ATPG vectors on tester hardware Master's Degree in Electrical or Computer Engineering

Expertise of using Cadence Modus DFT tools

Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus null

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion,sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military oruniformed service member status, or any other status or characteristic protected by applicable laws, regulations, andordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to ....