EDA Infrastructure Engineer

The MOSIS 2.0 PIES Team is Hiring

Background: The California Defense Ready Electronics and Microdevices Superhub (California DREAMS) will promote innovation and lab-to-fab transition for RF and other technologies in the Southern California region. MOSIS 2.0 will play a critical role in providing access to university nanofabs and industry prototyping and production fabs in support of rapid prototyping for Government- and Industry-funded R&D projects. The primary end uses for the service span from advanced RF-spectrum communications and sensing applications such as 5G/6G and related domains to advanced digital design, 2.5D chiplet designs, and emerging 3D designs. The Prototype Integration and Engineering Services (PIES) team will operate within MOSIS 2.0 to provide engineering support for users bridging the valley between innovations and production.

MOSIS 2.0 PIES team is hiring an EDA Infrastructure Engineer that will be part of a core team at USC/ISI complemented by a distributed team at our partner university labs and industry fabs.

Location:

California (On-site at the USC University Park Campus)

Position Type:

Full-Time, Research/Support Role, MOSIS 2.0 (California DREAMS Microelectronics Commons) / USC ECE Department.

Key responsibilities:

• Maintaining EDA tool flows for tools from multiple vendors, with an emphasis on digital flows
• Managing cloud platform for EDA tool usage and IP repository
• Support internal and external EDA users
• Supporting collaborative cloud-based EDA ecosystem for hub and inter-hub use

MOSIS 2.0 is looking for a team member with experience in the following:

• Experience using and developing flows for tools from Ansys, Cadence, Keysight, Siemens, and Synopsys tools (not all five required but experience across vendors desired)
• Experience with deployment and use of EDA tools on commercial cloud platforms
• Experience with analog and digital design
• Experience with IP module maintenance and usage

Requirements: Minimum of master's level degree in electrical engineering, materials science, physics, or related degree covering fundamentals of microelectronics engineering principles and fabrication technologies and five years of experience with a variety of EDA flows from a variety of vendors. Experience spanning analog and digital design and IP development, usage, and maintenance.

Given there is some need for standard CMOS I might emphasize the users span both analog and digital designers

I might mention that we expect this person to help develop a collaborative EDA ecosystem across the hub that covers not only licenses but sharing of tool expertise and experiences.

The annual base salary range for this position is $156,918 - $180,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate's work experience, education/training, key skills, internal peer equity, federal, state and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations.

Minimum Education: Master's degree

Addtional Education Requirements Combined experience/education as substitute for minimum education

Minimum Experience: 3 years

Minimum Skills: Working knowledge of electrical and computer engineering.

Preferred Education: Doctorate

USC is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other characteristic protected by law or USC policy. USC observes affirmative action obligations consistent with state and federal law. USC will consider for employment all qualified applicants with criminal records in a manner consistent with applicable laws and regulations, including the Los Angeles County Fair Chance Ordinance for employers and the Fair Chance Initiative for Hiring Ordinance, and with due consideration for patient and student safety. Please refer to the Background Screening Policy Appendix D for specific employment screen implications for the position for which you are applying.

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