Principal Systems Design Engineer, HBM

Responsible for floorplanning the full chip level. Responsible for design partitioning. Responsible for top level synthesis with multiple hard macro IP blocks. Responsible for developing automate high speed matching routing. Perform verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership qualities in planning, area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. 6 to 9 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Significant experience with industry APR tools like Innovis or Fusion Compiler Good understanding of Analog Layout fundamentals (e.cg., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc. Ability to understand design constraints and implement high-quality layouts Ability to understand design hierarchy and different architectures for Memory designs. Excellent problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Excellent verbal and written communication skills.