Fullchip Floorplan Design Engineer

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At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

T HE ROLE :

As part of AMD’s S3 (Semi-Custom) organization, you will work within the Physical Design integration team to translate SoC RTL into a full-chip floorplan, enabling downstream implementation and first-pass silicon success. This role operates at the intersection of architecture, RTL, DFT/DFX, and physical design, with a primary focus on defining chip-level structure early in the design cycle. It is a highly hands-on, execution-driven role requiring deep expertise in full-chip floorplanning and physical design.

THE PERSON:

You are a hands-on physical design engineer with strong experience in full-chip floorplanning and SoC implementation. You are comfortable working across teams, driving early-stage implementation decisions, and translating design intent into practical physical structures. You bring strong ownership, problem-solving ability, and consistently deliver high-quality results in fast-paced, technically complex environments.

K EY RESPONSIBLITIES :

• Own full-chip floorplanning (partitioning, macro placement, integration)
• Translate RTL → full-chip floorplan (chip structure, block definition)
• Plan pins, feedthroughs, and bus topology (incl. source-synchronous interfaces)
• Define repeater strategy for timing and signal integrity
• Optimize floorplan for timing, power, and area (PPA)
• Run feasibility / tradeoff analysis for floorplanning decisions
• Collaborate with RTL, architecture, DFT/DFX, and PD teams
• Use tools like Fusion Compiler / Innovus for implementation
• Build automation (Tcl / Perl / Python) to improve execution

P REFERRED EXPERIENCE :

• Experience in SoC physical design with successful tapeouts
• Strong ownership of full-chip floorplanning (partitioning, macro placement, integration)
• Solid understanding of physical design flows and impact on timing, power, and implementation
• Hands-on experience with Fusion Compiler or similar tools (e.g., Innovus)
• Experience with feedthrough planning, bus topology, and timing-aware floorplanning
• Understanding of SoC architecture (e.g., AXI, source-synchronous interfaces, test)
• Proven collaboration with RTL, IP, DFT/DFX teams
• Scripting skills (Tcl, Perl, Python, or Shell) for automation
• Experience with large-scale SoC designs and low-power considerations
• Experience improving design productivity through automation or advanced methods

ACADEMIC CREDENTIALS:

• Bachelor's or master’s degree in electrical engineering, computer engineering, or related field preferred

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Benefits offered are described: AMD benefits at a glance .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.