Physical Design Engineer V
Colorado Springs, Colorado; United States
Engineering
8201
Job Description
For more than six decades, the skilled thinkers, makers, and doers at Frontgrade have embraced our mission to solve complex technology challenges across the U.S. and around the globe.
We're the leading provider of high reliability and radiation assured solutions for defense, space, intelligence, commercial, and civil applications, and our products are designed to perform in the harshest of environments. From human spaceflight and space exploration to missile defense, electronic warfare, and healthcare tech advancements, our talented team stays in lockstep with our customers to ensure the success of their missions.
Do you want to help shape the future? In an environment where innovation and ideas go hand-in-hand? Then come join the Frontgrade Team!
Why Work For Us
We take care of our people and provide competitive health, wealth and wellbeing benefits - from day one. You'll also discover learning and development opportunities so you can take your career to the next level - and beyond.
Other benefits include:
Competitive Benefits: Medical (FSA + HSA), Dental, and Vision
Immediate 401K Vesting/Matching
Career Opportunity and Growth
Tuition Reimbursement
Student Loan Repayment
Generous PTO and 11 paid Holidays per year (8 regular and 3 floating)
8 weeks of 100% Paid Family Leave
Overview
The Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release. The candidate should have a high aptitude for design, floorplan and IO planning of complex digital top level and blocks, with experience across the complete ASIC/SOC design flow including routing, clock tree and CTS, static timing closure, EM/IR analysis and chip finishing (physical verification). The individual will closely collaborate with other digital design engineers, customers, place and route designers and supporting engineers.
Responsibilities
KEY RESPONSIBILITIES
Floor-planning of moderate to very complex integrated circuits, including die sizing, Block, macro and IO placements.
Understanding of multi-corner multi-mode (MCMM) optimizations.
Creating power and ground distribution networks and applying unified power format (UPF.)
Constraining and synthesis of clock trees (CTS.)
Running routing optimization, congestion analysis and route-ability checks.
Support of static timing analysis (STA) and execution of an engineering change order (ECO.)
Support of technical presentations for both internal and external customers.
Proficiency with Synopsys EDA tools, especially IC Compiler II
Qualifications
QUALIFICATIONS & EXPERIENCE
Minimum ten (10) years of direct industry experience in ASIC and/or SoC design.
OR (14) years of experience may be considered in lieu of a Bachelors Degree.
OR (8) years of experience may be considered w/ a Masters Degree.
OR (5) years of experience may be considered w/ a PhD.
Bachelor's degree in Electronic or Electrical Engineering/Computer Science
A strong background in physical integrated circuit design and transistor layout architectures.
Use of modern revision-control tools.
Performing post-layout power analysis to include EM & IR drop.
Experience with place & route, clock tree synthesis, timing closure, decap & filler cell insertion, density fill methodologies, DFM, and EM/IR methodologies.
ADDITIONAL INFORMATION
This position requires access to technology, materials, software or hardware that is controlled by either ITAR or EAR U.S. export laws. As a condition to this job offer, in order to be employed in this position, you must be able to obtain an U.S. Government export license(s), as required by law.
Pay Range: $147,000 - $187,000 annually. Applicable pay within the posted range may vary based on factors including, but not limited to, geographical location, job function of the position, education, and experience of the successful candidate.
WE ARE AN EQUAL OPPORTUNITY EMPLOYER
We welcome differences and celebrate new ideas. We believe the diversity of our people inspires our creativity and drives our innovation. Everyone is welcome here, regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status, or genetic information.
We are committed to working with and providing reasonable accommodations to individuals with disabilities. If you need a reasonable accommodation due to a disability for any part of the employment process, please email ....
If you have relevant skills that are not reflected in your resume, we welcome your application and encourage you to share more in an optional cover letter or to join our Talent Community Connect Portal - Connect (icims.com).
Colorado Springs, Colorado; United States
Engineering
8201
Job Description
For more than six decades, the skilled thinkers, makers, and doers at Frontgrade have embraced our mission to solve complex technology challenges across the U.S. and around the globe.
We're the leading provider of high reliability and radiation assured solutions for defense, space, intelligence, commercial, and civil applications, and our products are designed to perform in the harshest of environments. From human spaceflight and space exploration to missile defense, electronic warfare, and healthcare tech advancements, our talented team stays in lockstep with our customers to ensure the success of their missions.
Do you want to help shape the future? In an environment where innovation and ideas go hand-in-hand? Then come join the Frontgrade Team!
Why Work For Us
We take care of our people and provide competitive health, wealth and wellbeing benefits - from day one. You'll also discover learning and development opportunities so you can take your career to the next level - and beyond.
Other benefits include:
Competitive Benefits: Medical (FSA + HSA), Dental, and Vision
Immediate 401K Vesting/Matching
Career Opportunity and Growth
Tuition Reimbursement
Student Loan Repayment
Generous PTO and 11 paid Holidays per year (8 regular and 3 floating)
8 weeks of 100% Paid Family Leave
Overview
The Physical Design Engineer will be responsible for taking ownership of the physical chip development, executing from the inception of the design (RTL or gate netlist) through the tape-out release. The candidate should have a high aptitude for design, floorplan and IO planning of complex digital top level and blocks, with experience across the complete ASIC/SOC design flow including routing, clock tree and CTS, static timing closure, EM/IR analysis and chip finishing (physical verification). The individual will closely collaborate with other digital design engineers, customers, place and route designers and supporting engineers.
Responsibilities
KEY RESPONSIBILITIES
Floor-planning of moderate to very complex integrated circuits, including die sizing, Block, macro and IO placements.
Understanding of multi-corner multi-mode (MCMM) optimizations.
Creating power and ground distribution networks and applying unified power format (UPF.)
Constraining and synthesis of clock trees (CTS.)
Running routing optimization, congestion analysis and route-ability checks.
Support of static timing analysis (STA) and execution of an engineering change order (ECO.)
Support of technical presentations for both internal and external customers.
Proficiency with Synopsys EDA tools, especially IC Compiler II
Qualifications
QUALIFICATIONS & EXPERIENCE
Minimum ten (10) years of direct industry experience in ASIC and/or SoC design.
OR (14) years of experience may be considered in lieu of a Bachelors Degree.
OR (8) years of experience may be considered w/ a Masters Degree.
OR (5) years of experience may be considered w/ a PhD.
Bachelor's degree in Electronic or Electrical Engineering/Computer Science
A strong background in physical integrated circuit design and transistor layout architectures.
Use of modern revision-control tools.
Performing post-layout power analysis to include EM & IR drop.
Experience with place & route, clock tree synthesis, timing closure, decap & filler cell insertion, density fill methodologies, DFM, and EM/IR methodologies.
ADDITIONAL INFORMATION
This position requires access to technology, materials, software or hardware that is controlled by either ITAR or EAR U.S. export laws. As a condition to this job offer, in order to be employed in this position, you must be able to obtain an U.S. Government export license(s), as required by law.
Pay Range: $147,000 - $187,000 annually. Applicable pay within the posted range may vary based on factors including, but not limited to, geographical location, job function of the position, education, and experience of the successful candidate.
WE ARE AN EQUAL OPPORTUNITY EMPLOYER
We welcome differences and celebrate new ideas. We believe the diversity of our people inspires our creativity and drives our innovation. Everyone is welcome here, regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status, or genetic information.
We are committed to working with and providing reasonable accommodations to individuals with disabilities. If you need a reasonable accommodation due to a disability for any part of the employment process, please email ....
If you have relevant skills that are not reflected in your resume, we welcome your application and encourage you to share more in an optional cover letter or to join our Talent Community Connect Portal - Connect (icims.com).
Job ID: 484254128
Originally Posted on: 7/6/2025
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