RTL Design Engineer

Hybrid or remote options

Description:

JOB DUTIES:

• Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend Analog Macro level architectural specification.

RTL Candidate Requirements

Top 3 skills:

• Modelling Analog-Mixed signal circuits in RTL, with experience in LDOs, BGs and EMC
• Ability to run and debug LECC for design
• Run quality check tool such as Spyglass Lint and fix issues.

• Ability to provide direction on optimal/efficient hierarchical design of Analog-Mixed signal designs
• Ability to run Co-Sim preferred
• Ability to debug DV issues preferred

Experience:

• 7+ years' experience required

Education:

• Bachelor's (required) or Master's in Computer Engineering

Notes:

Hybrid or remote options

VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status