Soc/Asic Design Engineer

zeroRISC zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility.Led by the founders of the OpenTitan secure silicon project, zeroRISC is driving commercial adoption of high assurance software and services rooted in open silicon.Our products forge an immutable connection between hardware and software, enabling users to trust their devices no matter where they're built or where they're deployed.Role Overview As a zeroRISC SoC/ASIC Design Engineer, you will design and deliver new high-quality secure silicon at both the top and block level.You will accelerate adoption of zeroRISC products by refining new and existing designs and making the integration process even more seamless.You will interact directly with customers to understand their requirements and deliver solutions benefitting both customer and zeroRISC alike.You will participate in the whole chip design process from architecture to tapeout and silicon validation.By engaging with the world's premier open-source silicon community, you will support our mission of open secure silicon everywhere.We're looking for engineers with strong hardware design skills (and a long view of secure system architecture) who are also fast, flexible learners and enthusiastic about open source.Key ResponsibilitiesDesign ASICs/SoCs at the chip/top and block level a balancing functionality, performance, power, area, and schedule a throughout the full chip design life cycle from architecture definition to sign-off and post-silicon validationWrite thorough design specificationsAuthor high-quality SystemVerilog following engineering best practicesParticipate with verification team on test plan definition, debug, and coverage closureEnsure high-quality full-system design functionality while upholding stringent timelines in collaboration with architecture, verification, physical design, test, software, system, emulation, and silicon validation teams, as well as engineering program managersWhat We're Looking For:Bachelor's degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience4 years of experience with architecture and design of SystemVerilog-based chips and IP blocksExperience with design flows including lint, synthesis and timing closure (e.g.SDF)Experience with multipower and multiclock domain designsPreferred Qualifications (not required):Master's or PhD in Electrical Engineering or Computer Science, or a related technical field or equivalent experienceKnowledge of security ASICs or accelerators (e.g.cryptography accelerators or GPUs)Knowledge of computer architecture and memory subsystem architecturesExperience designing standard components such as ALUs and caches and standard interfaces such as USB and I2CExperience with IP block integrationExperience with UPF and power analysis and estimationExperience with CDC and RDCExperience with DFD, DFT, and design for verificationExperience with FPGA and emulation platformsExperience with assertion codingExperience with scripting languages such as PythonWhy Join Us?Your work will directly contribute to the development of cutting-edge security solutions, protecting critical systems in industrial and IoT environmentsAs a seed-stage startup, this role offers significant opportunities for learning and career growthJoin a close-knit, innovative team where you can learn, grow, and contribute to building something meaningful in the security space#J-18808-Ljbffr