AR Subsystem Performance Architect, Reality Labs Silicon

As a member of the RL subsystem architecture team you will play a key role in performance architecture and modeling. You will analyze our key workloads (graphics rendering, display, audio, computer vision, or color imaging) and collaborate with IP architects and execution engineers to architect subsystems that are SW usable, performant and power efficient. You will also act as a key point-of-contact representing the team with varying internal and external partners, in a highly cross-functional environment, delivering on proof of concepts for workloads and other significant demands.

Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of performance modeling experience with programming (C/C++ or SystemC-TLM) and scripting (Python) 5+ years of experience evaluating architectural trade-offs in performance, power, and other key performance metrics 4+ years of expertise with post-silicon to pre-silicon correlation analysis 2+ years of experience with System on Chip (SoC) Architecture, NoCs, memory subsystems, and heterogeneous compute principles 3+ years of experience with bare-metal programming, micro-benchmarking, etc 3+ years of experience deconstructing a problem, designing performance experiments, analyzing and visualizing data, and drawing conclusions for modeling and subsystem architecture 2+ years of experience with power concepts and low power design principles Expertise collaborating and communicating effectively in a matrix environment, as well as taking initiative as the point-of-contact representing your team with internal and external partners Expertise in at least one relevant area: Audio, Display, Rendering, Computer Vision, or Imaging Expertise with developing and utilizing telemetry solutions to analyze and profile workloads

Responsibilities: Identify performance opportunities for optimization and collaborate with hardware teams to solidify Hardware-Software (HW-SW) co-design Own performance models for system interconnect, cache, memory hierarchy analysis Own Subsystem Network on Chip (NoC) architecture specification, design and characterization Lead Intellectual Property (IP) performance bottleneck analysis using traffic traces from pre/post silicon platforms Lead analysis and configuration of subsystem caches for optimal performance Drive next generation workload analysis for performance across the workloads of interest Drive IP latency hiding features and Quality of Service (QoS) recommendations for each compute engine Collaborate with various partners to deliver documentation and proof of concepts for workloads running on these subsystems Identify and manage appropriate comparative analysis to ensure the workloads are targeting state of the art