Digital Design Engineer - Reality Lab Silicon AI Research

We are looking for an experienced digital design engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and integrate advanced IP and AI accelerators into SOC/ASIC solutions to enable in-system testing and prototyping. The goal is to de-risk new IP/accelerators, prove out advanced compute/memory architectures and to harden controls/algorithms for next generation AI and AR solutions. As a Digital Design Engineer (DDE), you will be a key contributor in planning and executing our front-end digital design efforts at the IP and sub-system levels. Additionally, this role includes hardware and software codesign and supporting post silicon firmware development. From microarchitecture definition and RTL implementation to firmware development and system software, demonstrated fundamentals in digital design and C will enable you to contribute to all phases of the chip development. Additionally, effective collaboration and communication with Digital Design Engineers, Digital Verification Engineers, Research Scientists and XFN teams will be key to your success.

Qualifications: Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta 2+ years of experience as a Digital Design Engineer Proven communication and collaboration skills Knowledge of digital SoC integration and ASIC architecture Skilled in micro-architecture, RTL coding, design verification and SoC Integration of complex IPs Experience in CDC, SDC and STA Self-directed and detail oriented in all phases of Design Digital and firmware development BS Electrical Engineering or Computer Engineering Familiarity with low-power design techniques Master's degree in EE or CE Python (or similar) scripting experience Experience using C for system verification Familiar with IP, sub-system and SoC DV and ability to execute design verification working with DV lead Experience developing RTOS drivers in C Knowledge of common industry interfaces like AXI, APB, I3C, SPI, UART, etc Some familiarity with compute and/or memory architectures for ultra low power applications

Responsibilities: Contribute to microarchitectural feature definition, RTL design, design verification and project planning Deliver quality RTL in collaboration with Digital Verification (DV) Support back end physical design (PD) through STA and SDCs Develop system tests in C for custom hardware Help create and maintain design documentation including IP/SoC Micro Architecture document (collaborator/owner), IP/SoC Design plan (collaborator) and SoC/chip bringup/validation plan (collaborator)