FPGA/ASIC Design Engineer

5 yrs, FPGA design/debug, Xilinx FPGA / EDA-Vivado. Minimum 3 years of experience in hands-on multiple complex designs, arch/design/verification/Synthesis/STA. Preferred Skills / Qualifications: Master's Degree in Science or Electrical Engineering or Computer Science. High-Level Synthesis (HLS) with Vivado, Embedded SW C++ (OOP) and System Verilog Assertions (SVA) Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet) Excellent Analytical/debugging skills Good verbal, written, and presentation skills. Working with the Ethernet protocol (not just instantiating the IP). Mentor EDA CDC/Lint/AC/RDC. Additional Information: Upon offer of employment, the individual will be subject to a background check and a drug screen. Active Secret DoD Clearance In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Under the International Traffic in Arms Regulations (ITAR), all employees assigned to this client must provide documentation verifying their status as a 'U.S. Person,' as defined in ITAR clause 120.15. A U.S. Person is a protected individual under the anti-discrimination provisions of U.S. immigration laws. Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct) are equal opportunity employers. Race/Color/Gender/Religion/National Origin/Disability/Veteran. Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status.