Description:

JOB DUTIES:

1. Soft IP Development for client FPGA's using Verilog/System Verilog.
2. Integrate third party IP cores into an FPGA system, create custom RTL wrappers for third party cores, and interface with IP vendors
2. Work with Verification Engineers to verify IP and debug issues.
3. Participate in board bring up as well as system level integration.

EXPERIENCE AND EDUCATION :

7 to 12 years of experience in digital design
RTL coding experience using Verilog and/or System Verilog
Strong in digital design, micro architecture , RTL development
Working experience of client/Xilinx FPGA and Vivado
Experience in Video domain (DisplayPort/MIPI/HDMI/SDI) is preferred
Detailed understanding and proven track record of designing leading edge standard and proprietary high speed interfaces IPs/Solutions
Good understanding of system design aspects and its impact on performance and throughput

Notes :

Position is 100% remote

VIVA is an equal opportunity employer. All qualified applicants have an equal opportunity for placement, and all employees have an equal opportunity to develop on the job. This means that VIVA will not discriminate against any employee or qualified applicant on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability or protected veteran status