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Principal/Staff Design Engineer- Timing Expert
Regular Full-Time
US - Dallas, TX, Plano, TX, US
+1 More Locations
5 days ago
Requisition ID: 4476
Principal Engineer (Timing Expert): Perform independent integrated circuit level architecture definition, simulation and verification for design using CMOS technology with little or no supervision.
Principle Duties and Responsibilities:
Work as a key member in a development team, perform IC level architect on analog/digital circuit design and verification using deep submicron CMOS process technology. The individual need to carry out assigned design independently and mentor/monitor the execution of design team, need to supervise layout work and working with product engineering and test engineering for post silicon verification and product characterization.
The individual needs to define circuit structure and product architecture, need to carry the design from front end concept to back end physical implementation, and he/she is able to generate high level product model and provide occasional customer support.
Responsible for analog and digital design architecture and knowledgeable on building blocks for ultra-low jitter PLL, PFD Link, digital filter, Fraction N divider, open-loop FOD with SSC, higher performance output buffer.
The individual needs to work with both analog and digital team and define the signals between analog and digital interface, circuit block performance, run top level simulations and make sure the quality of final product.
The individual is able to create and verify the high-level model in Matlab describe system design/architecture.
The individual needs to create and maintain documentation for the related project work and may create and improve the design flow.
Knowledge, Skills and Abilities:
MSEE/PhD with a minimum 5 years' experience or BSEE with 7 years' experience.
Hands on in Cadence tool set, Synopsys tool set, Spectre & Hspice simulation tool, Matlab, and layout tools.
Ability to work as a team and able to work across other groups.
Language- Mandarin a plus not required
Principal/Staff Design Engineer- Timing Expert
Regular Full-Time
US - Dallas, TX, Plano, TX, US
+1 More Locations
5 days ago
Requisition ID: 4476
Principal Engineer (Timing Expert): Perform independent integrated circuit level architecture definition, simulation and verification for design using CMOS technology with little or no supervision.
Principle Duties and Responsibilities:
Work as a key member in a development team, perform IC level architect on analog/digital circuit design and verification using deep submicron CMOS process technology. The individual need to carry out assigned design independently and mentor/monitor the execution of design team, need to supervise layout work and working with product engineering and test engineering for post silicon verification and product characterization.
The individual needs to define circuit structure and product architecture, need to carry the design from front end concept to back end physical implementation, and he/she is able to generate high level product model and provide occasional customer support.
Responsible for analog and digital design architecture and knowledgeable on building blocks for ultra-low jitter PLL, PFD Link, digital filter, Fraction N divider, open-loop FOD with SSC, higher performance output buffer.
The individual needs to work with both analog and digital team and define the signals between analog and digital interface, circuit block performance, run top level simulations and make sure the quality of final product.
The individual is able to create and verify the high-level model in Matlab describe system design/architecture.
The individual needs to create and maintain documentation for the related project work and may create and improve the design flow.
Knowledge, Skills and Abilities:
MSEE/PhD with a minimum 5 years' experience or BSEE with 7 years' experience.
Hands on in Cadence tool set, Synopsys tool set, Spectre & Hspice simulation tool, Matlab, and layout tools.
Ability to work as a team and able to work across other groups.
Language- Mandarin a plus not required
Job ID: 478743760
Originally Posted on: 5/28/2025
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