Package Design Engineer

Meta is looking for an experienced ASIC Packaging Engineer, Signal Integrity, and Power Integrity focus for its ASIC packaging team to support the development of custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging technology to support the development of custom silicon and looking for expertise in hardware development and integration of machine learning clusters, both server and fabric with focus on the impact they can create as part of a world-class engineering team.Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Perform package design for advanced custom silicon comprising single-chip/multi-chip and 3D or wafer packaging. This includes: design feasibility studies and analyses, package design/layouts based on silicon chip IO, electrical performance and system ID/form factor requirements Participate in silicon architecture/package/PCB/system co-design work collaborating with downstream system design teams and upstream silicon designers to develop holistically optimal solutions Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for next generation versions of current products Lead package development to establish package manufacturability and reliability Collaborate with multi-functional teams with in Meta and define package requirements Perform package design for advanced custom silicon comprising single-chip/multi-chip and 3D or wafer packaging. This includes: design feasibility studies and analyses, package design/layouts based on silicon chip IO, electrical performance and system ID/form factor requirements Participate in silicon architecture/package/PCB/system co-design work collaborating with downstream system design teams and upstream silicon designers to develop holistically optimal solutions Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for next generation versions of current products Lead package development to establish package manufacturability and reliability Collaborate with multi-functional teams with in Meta and define package requirements