Senior Fabric Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior Fabric Design Engineer to join the team.

Required/minimum qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
• 4+ years of experience in digital logic design for ASIC or FPGA
• 4+ years of logic design flow experience including RTL coding, RTL simulation, synthesis, timing constraints, timing closure

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional Preferred:

• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting, etc).
• Demonstrated proficiency in Computer Architecture, Digital Design, CPU/SoC design principles as part of CPU, SoC and/or IP development
• Demonstrated experience and knowledge of design clock crossings and power/UPF.
• Ability to write scripts using Perl, Tcl, Python etc.
• Experience in building and integrating any of the IPs such as protocol bridges, PCIe, cache controllers, memory controllers and DDR, security engines.
• Experience in building functional fabrics using Coherent and Non-Coherent protocols.
• Familiarity with Industry standard interface protocols such as AXI or CHI.
• Familiarity with Synthesis and STA tools.
• Good verbal and written communication skills.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until July 25th, 2025.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

#AHSI #SCHIE

• Be part of a design team developing advanced components of the memory sub-system
• Own multiple blocks within a complex, coherent fabric, and bridge IP
• Drive efficiency in integration and automation of highly configurable IPs
• Be responsible for all aspects of the design flow including microarchitecture, RTL coding, Lint, CDC, timing closure, etc
• Collaborate with team members to define interfaces and make optimal design choices
• Work with the verification teams to develop test plans and ensure functional correctness
• Interface with performance modeling, physical design, design for test, and other teams to optimize tradeoffs