Senior Silicon Logic Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) Logic Design team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior Silicon Logic Design Engineer to join the team.

Required/Minimum Qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

• 4+ years logic design experience as a part of either CPU, Cache, Fabric, Compute Tile, Digital Power Management, PCMs, Debug, Peripherals and/or Subsystem and SoC development

• 4+ years logic design flow experience including RTL coding, Synthesis, timing constraints, timing closure.

• 4+ years years of experience in Computer Architecture, Digital Design, IP/SoC design principles as part of SoC and/or IP development.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Additional or preferred qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
• Highly Proficient in Verilog/System Verilog coding constructs.
• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
• Demonstrated experience and knowledge of clock crossings, and power/UPF in design
• Ability to write scripts using Perl, Tcl, Python etc.
• Familiarity with Industry standard interface protocols is a plus.
• Familiarity with Formal Equivalence Verification and Power Analysis is a plus.
• Good verbal and written communication skills.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until July 25th, 2025.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

#SCHIE #AHSI #azurehwjobs #CCDO #Logicdesign

In this role, you will be an integral part of the Logic Design Team, contributing to micro-architecture implementation, RTL coding, IP and subsystem development, and SoC integration, along with design quality assurance. Your responsibilities include:

• Implementing micro-architectural specifications in Verilog or SystemVerilog
• Expanding your micro-architectural knowledge and contributing to unit, subsystem, and SoC-level architecture
• Developing and integrating various functional block RTLs into SoC RTL
• Performing design quality checks such as timing closure, lint, CDC, synthesis, and low power intent
• Collaborating with the verification team to ensure functional correctness
• Interfacing with performance modeling, physical design, design-for-test, and other teams to deliver qualified physical partitions
• Writing basic tests and debugging features at IP and SoC levels as needed
• Automating tasks using scripting to improve efficiency
• Delivering high-quality functional blocks on schedule with professional integrity
• Challenging the status quo with a growth mindset
• Mentoring junior team members and summer interns as part of a growing team