Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners world wide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Microsoft’s Cloud Compute Development Organization (CCDO) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior Physical Design Engineer to join the team.

• Accountable for Design-for-Test (DFT) & Functional mode Timing Analysis and convergence within the Physical Design (PD) domain.
• Facilitate coordination across cross-functional teams, including DFT, RTL/Design/IP, Static Timing Analysis (STA), CAD, Architecture, Power & Performance, and both internal and external stakeholders.
• Drive execution of timing- and power-critical IPs with a focus on Power, Performance, and Area (PPA) optimization.
• Provide leadership and strategic direction in signoff timing and extraction methodologies, including tools, flows, and methodology (TFM).
• Experience in Synthesis to PD Signoff of partitions/blocks is considered a significant advantage.
• Exhibit comprehensive technical proficiency across all various sub-domains of Physical Design and End-to-End Timing Signoff.
• Comprehensive updates and strategic planning communications throughout the project lifecycle.
• Engage in cross-regional collaboration aligned with project and organizational needs.
• Exemplify Microsoft’s core values, including Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence Impact, Sound Judgment, and a commitment to Diversity and Inclusion.

Required/Minimum Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
• 4+ years of experience in production design tape outs & implementing PPA (Power, Performance and Area) solutions with deep understanding of E2E DFT-Functional Timing Analysis & Convergence Physical Design domain.

Other Qualifciations:

• The ability to meet Microsoft, customer and/or government security screening requirements is required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• Extensive experience in large-scale SoC, CPU, and IP design tape-outs utilizing advanced foundry process nodes.
• Deep expertise in DFT-Physical Design (PD) architecture, including DFT modes and methodologies, with comprehensive experience in Static Timing Analysis (STA) for complex hierarchical SoC/CPU designs.
• Expertise in Engineering Change Order (ECO) implementation for power/timing convergence. Solid grasp of Timing (Functional and DFT) ECO closure methodologies is essential.
• Collaborate closely with Physical Design engineers to proactively identify and address DFT and functional architectural challenges, clocking strategies, global bus planning, and RTL/architecture feedback across various milestones.
• Proficient in understanding functional and DFT constraints, performing STA, driving timing optimization, and achieving timing closure.
• Thorough understanding of design trade-offs across power, performance, and area (PPA).
• Hands-on experience with industry-standard EDA tools such as Synopsys, and Cadence tool suites.
• Partner effectively with PD, DFT, STA flow, CAD teams, and EDA tool vendors to ensure seamless integration and execution.
• Demonstrated ability to take full ownership of individual deliverables while contributing collaboratively across teams.
• Proven track record in mentoring, cross-functional collaboration, and influencing teams through clear and effective communication.
• interpersonal skills with a commitment to fostering diverse and inclusive team environments.
• Exceptional problem-solving and data analysis capabilities.
• Proficient in automation and scripting using languages such as Perl, TCL, and Python.
• Great communication, collaboration and teamwork skills and ability to contribute to D&I

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Microsoft will accept applications for the role until July 25th, 2025.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

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